Creating a Single SDC File for Cadence SoC Encounter and PKS, Pre- and Post-CTS

This is an old, old post, but over the years it continues to be one of my most popular pages. I leave it here in the hope that it is still useful. Please add your corrections or comment. –John

It is good design practice to use as few SDC files as possible. This post describes a way to create a single SDC file that can be used both before and after clock tree synthesis (CTS), and by both Cadence PKS and SoC Encounter.

Test Mode SDC File

You will still need at least one more test mode SDC file for use when fixing test mode hold violations. You can put the design into test mode in SoC Encounter 3.1 only with set_case_analysis contained in a separate, full SDC file. The design can be put into test mode in PKS dynamically using the set_constant_for_timing command, but I have not actually tried this.

Functional Mode SDC File

Define the clocks as propagated. For example,

set_propagated_clock {clk200 txclk rxclk}

Create a virtual clock for each clock that appears in set_input_delay or set_output_delay. For example,

create_clock -name clk200v -period 5 -waveform {0 2.5}
create_clock -name txclkv -period 5 -waveform {0 2.5}
create_clock -name rxclkv -period 5 -waveform {0 2.5}

Usually, timing paths between clock domains are marked as false paths in the SDC file (if there is only one clock in your design , there will be no such false paths). Add set_false_path,

  • From each virtual clock to each real clock
  • From each real clock to each virtual clock

For example, suppose that false paths between the real clock domains are already defined in the SDC file as follows:

set_false_path -from [get_clocks {clk200}] -to [get_clocks {txclk}]
set_false_path -from [get_clocks {clk200}] -to [get_clocks {rxclk}]
set_false_path -from [get_clocks {txclk}] -to [get_clocks {tclk200}]
set_false_path -from [get_clocks {rxclk}] -to [get_clocks {tclk200}]

Add the corresponding false paths to and from the new virtual clocks:

set_false_path -from [get_clocks {clk200v}] -to [get_clocks {txclk}]
set_false_path -from [get_clocks {clk200v}] -to [get_clocks {rxclk}]
set_false_path -from [get_clocks {txclkv}] -to [get_clocks {tclk200}]
set_false_path -from [get_clocks {rxclkv}] -to [get_clocks {tclk200}]

set_false_path -from [get_clocks {clk200}] -to [get_clocks {txclkv}]
set_false_path -from [get_clocks {clk200}] -to [get_clocks {rxclkv}]
set_false_path -from [get_clocks {txclk}] -to [get_clocks {tclk200v}]
set_false_path -from [get_clocks {rxclk}] -to [get_clocks {tclk200v}]

Define network latency for the original clock and source latency for the virtual clock. Use the same value for both. This latency is your estimate of the clock latencies in the surrounding blocks, not the current block. Even so, it is quite common to use the latency for the clock in this block as a best guess of the clock latencies in other blocks.

set_clock_latency 2.0 [get_clocks {clk200}]
set_clock_latency -source 2.0 [get_clocks {clk200v}]

The -network option is the default, so it it omitted. Here, we are guessing that the surrounding blocks will eventually contain a clock tree with an insertion delay of 2.0nS.

Change the reference clocks for the input and outputs to the virtual clock. For example,

set_input_delay 2.5 -clock [get_clocks {clk200v}] [get_ports {garbageIn}]
set_output_delay 2.5 -clock [get_clocks {clk200v}] [get_ports {garbageOut}]

This is equivalent to changing the delays to set_input_delay 4.5 and set_output_delay 0.5. It is however, much more convenient to adjust a single set_clock_latency than to add and subtract delays to all IO pins.

Specify cells that you do not want to be used as set_dont_use.

set_dont_use TLATNX20
set_dont_use TLATNXL

Note that this is a less restrictive list than the list used during logic synthesis. During logic synthesis, cells like clock buffers, clock gate cells, delay cells, and scannable flip-flops are usually marked as dont_use, but not here.

This article was originally published by John McGehee, Voom, Inc. under the CC BY 3.0 license. Changes have been made.